The following references are known as examples of references each of which has described a semiconductor integrated circuit having bump electrodes used for circuit substrate implementation.
(a) Unexamined Patent Publication Hei 5 (1993)-218042, (b) Unexamined Patent Publication Hei 8 (1996)-250498 and (c) U.S. Pat. No. 5,547,740 respectively show one basic form of a flip-chip type semiconductor integrated circuit mentioned in the present specification. Namely, the flip-chip type semiconductor integrated circuit is configured as follows. For example, relocation wirings are routed from bonding pads of its chip, bump electrodes respectively connected to the relocation wirings are laid out on the surface of the chip in array form (in area array form), and the bump electrodes arranged in area array form are exposed from a surface protection film. It is thus possible to enlarge the interval between the bump electrodes, facilitate substrate mounting that the bump electrodes are respectively connected to wirings for a printed circuit board and utilize a low-cost printed circuit board in which wiring intervals are wide.
In the flip-chip type semiconductor integrated circuit, the bump electrodes are terminals capable of being directly mounted or implemented on a circuit substrate and are equivalent to external connecting terminals such as lead pins or the like for a package. After the bump electrodes are formed and wafer processes are all completed, only the bump electrodes are exposed and the bonding pads are finally covered with an insulating film or a protection film.
The present inventors have compared the number of the bonding pads in the semiconductor chip with the number of the external terminals (bump electrodes) typified by the lead pins for the package. According to the comparison, bonding pads used only for probe inspection and bonding pads connected to power terminals or the like by a technique for a bonding option are not assigned external terminals dedicated therefor. Thus, when the flip-chip type semiconductor integrated circuit is substituted for the semiconductor integrated circuit, a wafer probe test can be performed through the use of all bonding pads if it is antecedent to the formation of the relocation wirings and bump electrodes. However, it has been found out by the present inventors that there is a fear that when a probe is brought into direct contact with each bonding pad, the bonding pad is endamaged and a failure in connection to each relocation wiring occurs.
Techniques for probe testing are not described in the References (a) through (c) at all. The technology of forming under bump metals or metallurgies on bonding pads after having been subjected to probe testing or inspection, has been described in, for example, (d) Michael J. Varnau: “Impact of Wafer Probe Damage on Flip Chip Yields and Reliability”, International Electronics and Manufacturing Technology Symposium (Oct. 23-24, 1996) as a reference in which the relation to the probe inspection has been described. As to the reference described in the paragraph (d), however, there is a possibility that when a probe is applied to one of bonding pads antecedent to a relocation wiring process, the surface of the bonding pad will damage and the reliability of connection to a relocation wiring layer will be degraded, as discussed above by the present inventors. A limitation is imposed on the selection of a relocation wiring material.
Further, the following References are known as to the probe tests performed in the flip-chip type semiconductor integrated circuit.
(e) The technology of applying a probe to each under bump metal or metallurgy (UBM) antecedent to the formation of bump electrodes to perform a probe test has been described in U.S. Pat. No. 5,597,737.
(f) A configuration wherein testing pads are provided so as to adjoin under bump metallurgies and be connected thereto, has been shown in Unexamined Patent Publication No. Hei 8 (1996)-64633. The testing pads are respectively provided at the sides of bump electrodes.
(g) Unexamined Patent Publication No. Hei 8 (1996)-340029 shows a description related to the invention wherein portions directly above bonding pads at which relocation wiring layers are formed, are exposed and testing pads for probe inspection are formed at their exposed portions.
(h) Unexamined Patent Publication No. Hei 8 (1996)-29451 shows a description related to the invention wherein each of pads for probe testing is formed by a relocation wiring layer in the neighborhood of each bonding pad.
The present inventors could obtain the following results by further discussing the technologies described in the References referred to above.
It has been revealed by the present inventors that the technology described in the paragraph (e) also has the possibility that each under solder bump metallurgy will be endamaged at a probe tip in a manner similar to the technology described in the paragraph (d) and has led to degradation in wettability relative to solder and degradation in reliability of connections to each solder bump electrode due to the damage of a barrier metal used for the prevention of solder diffusion.
Further, the under bump metallurgies are placed in area array form in a manner similar to the bump electrodes in the technology described in the paragraph (e). In the technology described in the paragraph (f) the testing pads are also laid out in area array form together with the bump electrodes. Therefore, it has been revealed by the present inventors that each of the technologies described in the References (e) and (f) has a new problem in that it is difficult to apply a normally-used cantilever type probe to under bump metallurgies or testing pads arranged in a multiple row, and terminal-dedicated expensive probes disposed in area array form are additionally required.
It has been found out by the present inventors that the Reference described in the paragraph (g) has a problem in that when the size of each bonding pad and the interval between the bonding pads become narrow with high integration of a semiconductor device, the sizes of the testing pads and the interval therebetween become also narrow, and the positioning of each probe and reliable contact thereof fall into difficulties.
It has been revealed by the present inventors that the technology described in the paragraph (h) has the fear that since the area of each testing pad is added to its corresponding relocation wiring layer, the capacitance of a wiring increases and the electrical characteristic of a semiconductor integrated circuit is degraded.
It has been revealed by the present inventors that each of the References described in the paragraphs (f) through (h) is accompanied by a problem that since the testing pads are formed on an inorganic insulating layer or a metal wiring layer, the surface of each testing pad is hard to deform where a hard metal film such as chromium, nickel or the like is used for the testing pads, and hence the contactability with a probe tip is poor, and an expensive probe whose tip is given gold plating and which has adopted a structure capable of obtaining a wide contact area, is required.
Further, as described as the prior arts in the paragraphs (e) through (h), a problem has been revealed that when the probe is applied to the already-formed solder bump, the probe is applied to a curved surface covered with a thick oxide film under a strong load, whereby the bump is apt to deform and the probe per se is easy to undergo damage.
While the aforementioned References have described the flip-chip type semiconductor integrated circuit and the testing pads paired with the bump electrodes in this way, they do not show any description or suggestion that has taken into consideration the fact that the bonding pads used only for probe inspection and the bonding pads or the like connected to the power terminals or the like by the technique for the bonding option are not assigned the external terminals like the lead pins dedicated therefor as firstly discussed by the present inventors. Namely, the prior arts do not lead to the provision of the inventive concept that focused attention on the testing pads dedicated for testing, which are used only for probe testing or inspection and unnecessary at the final product stage. The testing pads always exist so as to pair with the bump electrodes. In other words, signals necessary for testing are set on the precondition that they are capable of being taken from the bump electrodes. Thus, the present inventors have revealed that if the solder bump electrodes are provided even for signal terminals necessary only for testing, then the number of the bump electrodes increases and the layout of the bump electrodes at practical intervals falls into difficulties from the meaning of mounting thereof to a circuit substrate.
An object of the present invention is to provide a semiconductor integrated circuit capable of executing a probe test without damage to pads antecedent to a relocation wiring process and without an increase in the number of bumps, and a manufacturing method thereof.
Another object of the present invention is to provide a semiconductor integrated circuit capable of reducing an increase in capacitance of each wiring, which is caused by the addition of a testing pad, and a manufacturing method thereof.
A further object of the present invention is to provide a semiconductor integrated circuit capable of enhancing contactability of a probe with each of testing pads, and a manufacturing method thereof.
A still further object of the present invention is to provide a semiconductor integrated-circuit capable of improving reliability of connections to a printed circuit board and reducing substrate mounting costs because a bump-to-bump interval can be taken wide, and a manufacturing method thereof.
A still further object of the present invention is to provide a semiconductor integrated circuit capable of reducing capacitive loads developed by metallic wirings for laying out protruding electrodes in array form.
The present inventors have discussed even a program element together with the flip-chip type semiconductor integrated circuit. In a semiconductor integrated circuit, the program element is used for relief or the like for substitution of a defective or faulty circuit portion thereof with a redundant circuit. As the program element, a fuse comprised of, for example, a metal film or a polysilicon film is heavily used and programmed by the melting thereof by irradiation with laser light. A program relative to the fuse is executed after the completion of a probe test. In this stage, openings for exposing bonding pads and fuses have been defined in a passivation film on the surface of a wafer. For example, the probe test is carried out by using the bonding pad, for example. The laser light is selectively applied to each fuse in such a manner that the location of a defect is found out upon the probe test and the defective portion is substitutable with a relieving circuit, whereby the program for the fuse is carried out.
An electric fuse is known as another program element. For example, U.S. Pat. No. 5,110,753 has described a technology wherein an antifuse corresponding to a kind of electric fuse is used for defective relief or the like of a DRAM. The antifuse has a configuration capable of being programmed by dielectric breakdown of an oxide film held in an insulating state. Further, U.S. Pat. No. 5,742,555 has shown, as an example of an antifuse, an example in which an oxide film is used to form a capacitor in a p-type well region, and a negative voltage is applied to a well electrode of the capacitor and a positive voltage is applied to a plate electrode on the oxide film to thereby bring a gate oxide film into dielectric breakdown. As other references each having described a semiconductor integrated circuit using an electric fuse, there are known U.S. Pat. No. 5,324,681, etc.
As other program elements, there are known non-volatile storage elements each capable of reversibly changing a programmed state, such as an electrically erasable programmable EEPROM, a flash memory, etc. U.S. Pat. No. 5,742,555 has described a DRAM having such a program element.
The present inventors have discussed the mounting program elements in the flip-chip type semiconductor integrated circuit for the purpose of defective relief, mode setting and trimming.
The firstly-discussed program element is a fuse capable of being blown by laser. A fuse (polysilicon fuse) comprised of a polysilicon film is shaped in rectangular form over an element isolating region provided in a well region on a semiconductor substrate. One end of the fuse is connected to a source region of a selection transistor through metal wirings corresponding to plural layers, whereas the other end thereof is connected to a ground potential through its corresponding metal wiring. After an interlayer dielectric and a passivation film between the metal wirings corresponding to the plural layers are layered over the polysilicon fuse, the layered film is etched to define an irradiation window for the radiation of laser light and finally an insulating film having a thickness of 0.5 μm to 1 μm is left. When the polysilicon fuse configured in this way is blown, the laser light is applied thereto through the insulating film. For example, the width of the polysilicon film, a layout interval, and the width of the irradiation window for applying the laser light are designed so as to take 2 μm, 5 μm an 10 μm respectively. Applying He—Ne laser having an intensity of 1.5 μJ and a spot diameter of 6 μm at this time enables the polysilicon fuse to be blown.
It has however been revealed by the present inventors that the system for blowing the conventional polysilicon fuse by the radiation of laser light has the following problems.
The first problem is that the process of defining the window for applying the laser light therethrough is becoming very difficult. In a so-called system LSI product in which a large-capacity DRAM or the like is mixed with a high-speed logic circuit and an analog circuit, which have recently been progress on rapid market expansion in particular, the logic circuit needs to have metal wiring layers of five layers or more. Thus, since the thickness of the insulating film from the polysilicon fuse to the top passivation film reaches 5 μm or more, it is technically difficult to uniformly effect etching for leaving the insulating film to a thickness of about 0.5 μm at a fuse upper portion on the whole surface of the wafer. When the thickness of the insulating film at the fuse upper portion is left 1 μm or more, the incident intensity of laser light becomes weak and the melting-down or blowing of the fuse becomes insufficient. When the thickness of the insulating film at the fuse upper portion is thinned to 0.5 μm or less, there is in danger of the surface of the fuse being exposed depending on variations in the subsequent process treatment. Thus, the probability of failure occurrence that non-blown fuses will break, becomes high significantly.
The second problem is that the fuse cannot be blown by the conventional radiation of laser light from the viewpoint of the system of the manufacturing process in the flip-chip type semiconductor integrated circuit. In the conventional manufacturing process, a manufacturing process executed within a clean room in a wafer state is completed in a stage in which the formation of the passivation film for preventing moisture from entering an upper portion of each metal wiring layer has been completed. Afterwards, the assembly into a package is done after probe tests and relief have been carried out, followed by execution of the final selection. In the flip-chip type semiconductor integrated circuit on the other hand, the process from the formation of each metal wiring (relocation wiring) similar to a lead frame to the deposition of solder bump electrodes is carried out within the clean room in the wafer state after the formation of the passivation film in order to further reduce the manufacturing cost thereof. When the conventional system for blowing the fuse through the radiation of the laser light is applied to the flip-chip type semiconductor integrated circuit, the deposition and processing of each metal wiring for constituting the relocation wring similar to the lead frame at the upper portion of each blown fuse are performed, thereby resulting in unavoidance of degradation in reliability due to the corrosion of the polysilicon fuse and entrance of moisture from its corroded portion. Thus, the present inventors have found out the need for a system capable of electrically performing some kind of program in the flip-chip type semiconductor integrated circuit as an alternative to the system for blowing the fuse by the radiation of the laser light.
The third problem resides in that the polysilicon fuse needs a relatively large layout area. One fuse needs a layout area of at least 5×10 μm2. This becomes a big factor that determines the upper limit of the number of fuses.
Next, the present inventors have discussed even the adoption of an electrically writable and erasable non-volatile storage element as the program element. According to it, it has been revealed that when the number of the program elements may be low, a chip occupied area taken by peripheral circuits used for electrical writing or the like relatively increases and hence area efficiency becomes disadvantageous.
According to the result of discussions, the present inventors have found out superiority in adoption of the electric fuse such as the antifuse or the like as the program element for the flip-chip type semiconductor integrated circuit. At this time, the present inventors have further revealed that since the application of a voltage for dielectric breakdown to the antifuse is a process necessary only in manufacturing stage of the semiconductor integrated circuit, there is no room to provide dedicated bump electrodes for the purpose of dielectric breakdown under such circumstances that a large number of bump electrodes must be formed with a great increase in the scale of the semiconductor integrated circuit. Further, since the state of stress/distortion developed in the bump electrodes is transferred directly to a chip because the bump electrodes are used as terminals for circuit board mounting in the flip-chip type semiconductor integrated circuit, the present inventors have recognized the need for the provision of means for relaxing it.
The present inventors have further discussed a bonding option for the flip-chip type semiconductor integrated circuit from another standpoint. The bonding option is a technique for determining operation modes according to, for example, whether each of bonding pads assigned to operation mode setting electrodes of a semiconductor integrated circuit, for example, should be kept floating or connected to a power terminal. To which lead pin a predetermined bonding pad of a semiconductor chip should be bonded, may be selected upon assembly in the bonding option. However, the bump electrodes are used as the terminals mounted directly to the circuit substrate or board in the flip-chip type semiconductor integrated circuit and correspond to the lead pins for the package. Thus, the execution of the process like the bonding option is no longer physically impossible after wafer processes are all completed. In order to change each of bump electrodes to be connected to electrode pads like specific bonding pads, wiring patterns each extending from the electrode pad like the predetermined bonding pad to its corresponding bump electrode must individually be changed. On the other hand, the present inventors have taken recognition of a need to enable a flip-chip type semiconductor integrated circuit having completed such wiring patterns once to be functionally set subsequently with a view toward gaining versatility or usability equivalent to the bonding option.
An object of the present invention is to provide a flip-chip type semiconductor integrated circuit which does not give rise to degradation in reliability elicited by using a by-laser fusible fuse as a program element, and a method of manufacturing the same.
Another object of the present invention is to provide a semiconductor integrated circuit wherein electrodes required to electrically change the state of a program element employed in a flip-chip type semiconductor integrated circuit do not limit the number of protruding electrodes for other applications.
A further object of the present invention is to provide a semiconductor integrated circuit capable of relaxing the state of stress/distortion given to a semiconductor substrate through protruding electrodes in a flip-chip type semiconductor integrated circuit.
A still further object of the present invention is to provide a flip-chip type semiconductor integrated circuit capable of easily obtaining versatility equivalent to a bonding option with respect to function setting or the like, and a method of manufacturing the same.
A still further object of the present invention is to provide a manufacturing method of efficiently carrying out necessary function selection and relief accompanied by inspection and a change in the state of a program element to thereby allow the manufacture of a flip-chip type semiconductor integrated circuit.
The above, other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.